The Advanced Packaging Battle: TSMC's Monopoly, Intel's Challenge, and Amkor's Role as an Arms Dealer

The full text has previously been published on 404k Knowledge Planet

The Advanced Packaging Battle: TSMC Monopoly, Intel's Challenge, and Amkor’s Role as an Arms Dealer

The landscape of advanced packaging is shifting from TSMC's exclusive monopoly towards a dual-sourcing model. Intel's EMIB, with its rectangular panel format, has gained a structural advantage for ultra-large packaging, and external customer orders have pushed its advanced packaging revenue expectations to over $1 billion, making it the first credible second source.

Content Overview

The landscape of advanced packaging is shifting from TSMC's exclusive monopoly to dual sourcing. Intel's EMIB, thanks to its rectangular panel format, has achieved a structural advantage in ultra-large format packaging, and external customer orders have raised its advanced packaging revenue expectations above $1 billion, becoming the first credible second source.

TSMC's CoWoS-L is still limited by the size of the circular wafer, but maintains scale leadership through continuous capacity expansion. Ultimately, both sides will converge towards glass core substrates, at which point the gap may narrow. Amkor, through long-term agreements binding both TSMC and Intel, is positioned to take orders regardless of which format prevails, making it a structural winner.

The Advanced Packaging Battle: TSMC monopoly, Intel's challenge, and Amkor betting on both sides

Intel’s advanced packaging business has now become a credible supply source for the AI accelerator industry, while TSMC continues to expand capacity. Amkor serves both sides.

According to Vikram Sekar, advanced packaging has long been a single-horse race. Every leading AI accelerator worth discussing combines logic chips and high-bandwidth memory through TSMC’s CoWoS, a position TSMC has monopolized over the past three years.

According to TF’s recent estimates, industry CoWoS capacity could reach 200,000 wafers per month, with TSMC running about 120,000 wafers per month by the end of 2026, and ASE and Amkor only gaining a foothold as overflow providers, handling about 80,000 wafers per month. TSMC has been rapidly building out capacity to support CoWoS demand. Most large GPU chips are packaged by TSMC, while simpler processes like Vera CPUs and auto parts spill over to Amkor/ASE fab lines.

Intel’s EMIB is the first credible second source with real orders. AWS and Cisco have already shipped external chips on EMIB. SpaceX and Tesla became partners for Intel's Terafab project around the Q1 2026 earnings call. Reportedly, Google’s TPU v8e will use EMIB in the second half of 2027, and Apple, Microsoft, and NVIDIA are also being discussed as potential customers. CFO David Zinsner, in the last two calls, raised the outlook for Intel’s external advanced packaging business from several hundred million to over $1 billion and told CNBC he expects each customer could bring billions in revenue. For a business of this small size, surpassing $1 billion purely from packaging is a step change.

However, as orders flow to Intel, TSMC is still expanding CoWoS capacity. With AI accelerator advanced packaging sizes increasing, the competition comes to a crossroads again, and this time, the outcome will depend on what happens as the industry moves towards glass core substrates in the coming years.

Table of Contents:

• EMIB challenges CoWoS monopoly—a three-year run of packaging monopoly, and the orders that are breaking it.
• Deep dive into CoWoS-L and EMIB—the three variants of CoWoS, Intel’s bridging approach, and how it differs from TSMC’s.
• Where are the size constraints—the mathematical differences between circular wafers and panels, limiting CoWoS-L and unleashing EMIB.
• The convergence to glass core panels—why warpage and CTE are forcing both foundries toward glass.
• What it means for investors—winners and losers, and the OSATs that benefit no matter which side wins.
• TSMC CoPoS’ glass partners—missing names on the glass landscape.

Deep Dive: CoWoS-L and EMIB

Many online comparisons of CoWoS and EMIB do not precisely distinguish the specific forms of each technology, opening room for misinterpretation. Let’s clarify first.

• CoWoS-S is the initial version, using a monolithic silicon interposer. Beyond a certain size, it becomes very large and expensive. TSMC’s upper limit is about 3.3 reticle size, or 2,380 mm2.
• CoWoS-R replaces the silicon interposer with a cheaper organic RDL interposer. AWS’s Trainium 2/3 chips use this method. They lack the interconnect density of the silicon interposer, and size is also quite limited.
• The variant supporting the largest AI packages today, used by Blackwell and Rubin, is CoWoS-L. It currently scales to 5.5 reticle size, or 4,720 mm2, with plans to grow to 9.5 reticle size or 8,150 mm2 by 2027. TSMC’s roadmap stretches to 14 reticle sizes, or 12,000 mm2 by 2029.

TSMC’s CoWoS-L and Intel’s EMIB are based on the same principle: abandoning a complete silicon interposer and only using silicon bridges where fine pitch routing is needed, such as chip-to-chip or chip-to-HBM connections, with the rest using cheaper wiring methods.

• TSMC refers to its bridge structure as LSI, meaning Local Silicon Interconnect, which is the “L” in CoWoS-L, embedding these in the RDL interposer.
• Intel calls its bridge structure EMIB, or Embedded Multi-die Interconnect Bridge, embedding it directly in the organic packaging substrate.

Note the difference in bridge location: CoWoS-L’s RDL interposer is manufactured on a wafer, so it’s still subject to the 300mm wafer and reticle limitations—which is why CoPoS and glass panels are the next big thing. EMIB embeds the bridge in an organic substrate, skipping the wafer carrier, freeing it from wafer size constraints, and allows it to scale up by using a rectangular panel.

Below is the Intel EMIB roadmap by size.

Today, Intel's EMIB delivers 8 reticle size, or 6,860 mm2, therefore it has a size advantage over TSMC’s current 5.5. This is thanks to choosing an organic substrate in a rectangular format rather than manufacturing an RDL interposer on a round wafer. Intel commits to reaching 12X by 2028, and TSMC’s corresponding target is 14X, but we still have to wait to see who actually delivers, and at what reticle size multiplier.

In the meantime, we can try to make some predictions.

Where are the Size Constraints